Low temperature deposition of inorganic semiconductors used in industry typically yields amorphous and polycrystalline phases of the semiconductor. These phases tend to have significantly lower carrier mobility than can be realized in single crystal variants of the same semiconductor. For example, hydrogenated amorphous silicon is a ubiquitous material used in the LCD displays industry and the emerging solar cell industry. However electron carrier mobility in hydrogenated amorphous silicon is typically in the range of 0.3 cm2/V·s-1.2 cm2/V·s, depending on deposition conditions. Amorphous silicon may be re-crystallized, post deposition, using a technique called solid phase crystallization. The resulting nano and micro grained polycrystalline material might have mobilities between 10 cm2/V·s-250 cm2/V·s. However, this is still significantly below single crystal silicon mobilities of greater than 450 cm2/V·s. A similar pattern of deteriorating electronic performance is found in most semiconductors as the material goes from single crystal to poly-crystal to amorphous phases.
Future trends in the display/electronics industry suggest that future displays, solar cells and electronic products will be made on flexible/conformal substrates. This transition is seen as inevitable to service the ever-present need and desire to reduce the size, weight and cost of devices we use without sacrificing performance. A wide gamut of devices from displays, electronics, and sensors, to name a few, would benefit from methodologies that result in the mass production of ruggedized, light weight, portable, small form factor, less power hungry, and lower cost devices. Furthermore, new and novel markets and opportunities could be addressed and opened up if these devices could be made flexible and/or conformal.
Typical performance metrics used in gauging the efficacy of an active semiconductor device are: device mobility, device speed, and the amount of current the device might be able to carry. Device mobility is related and affected by a multitude of factors such as: raw mobility of the semiconductor material used as the channel layer, say for example in a thin film transistor (TFT), the nature of the semiconductor/dielectric interface making up the TFT, device architecture, etc. Device speed depends linearly on device mobility but inversely on the square of the distance between the source and drain electrodes of the TFT. Similarly, the current carrying capacity of a TFT depends linearly on device mobility but inversely on the distance between the source and drain electrodes of the TFT.
As is widely known, device scaling is a common technique used to enhance active semiconductor device performance. Given constant device mobility, engineers are continually trying to reduce the distance between the source and drain of a TFT to get higher performance. However, this reduction in source/drain distance is conventionally accomplished by using very sophisticated and very expensive photolithography/patterning techniques. Such techniques are unsuitable for very large area substrates, and/or flexible substrates and/or end products that target very low cost applications.
To circumvent these challenges, scientists are exploring a new type of transistor, coined the “pickup stick transistor.” In general, there are two basic type of pickup stick transistors. In the first type, nanotubes or nanorods/nanowires (hence the name “stick”) form the semiconducting channel layer by themselves, and, in the second type, the nanotubes or nanorods (both metallic and semiconducting) are dispersed into an organic semiconducting host.
The operational principle of these pickup stick transistors is based on the concept of percolating networks, which are created within the dispersion of individual single-wall carbon nanotubes and narrow ropes within an organic semiconducting host. These percolating networks are randomized, discontinuous pathways between which charge carriers (electrons and holes) move. Percolation theory has been used to explain the conduction mechanism in nano/micro-crystalline silicon. Nano/micro crystalline silicon coatings consist of nano/micro crystallites of silicon embedded in a hydrogenated amorphous silicon host.
Although the pickup stick transistor has shown promise, it has quite a few shortcomings. For example, the transistor uses carbon nanotubes (CNTs) and, therefore, is not inexpensive to manufacture. The CNTs are made ex-situ, so there is on-going concern with material purity, material refinement, etc. CNTs vary greatly in length, diameter, chirality, and composition (metallic versus semiconducting). The deposition techniques used (spin coating) produce a non-aligned, random assortment of 2-D and 3-D CNT networks. This inconsistency translates to large variations in transistor performances (thereby limiting their use in a practical device). Indeed, one of the papers on pickup transistors itself points out that the “ability to increase mobilities without lowering the on/off ratios, key for device fabrication, cannot be achieved with random [single-wall nanotube] networks.” Bo, et al., “Carbon Nanotubes-Semiconductor Networks For Organic Electronics: The Pickup Stick Transistor,” Applied Physics Letters 86, 182102 (2005), at 182102-3 (emphasis added).
The inversion layer formed in the semiconducting channel layer in transistors (when activated) typically extends to a very small depth (<20 nm, more typically <10 nm) below the dielectric/semiconducting channel interface. This inversion layer ultimately dictates the performance of the transistor. In the pickup stick transistors being researched, there is no means to control the density of CNTs per unit area or volume within this inversion layer. This again translates to large variations in performance between different transistors in a group.
As mentioned above, nanotubes/nanorods/nanowires are used for conventional pickup stick transistors. For example, CNTs used were 2 nm in diameter, and ˜1 micron in length. As is known, such high aspect ratio structures lead to significant electric field enhancement. The present inventor believes that this is the reason why these conventional pickup stick transistors see onset of shortages even at fairly large tube spacings. This is also pointed out in the above-mentioned publication: “A 1% threshold value for this transition, equivalent to a 30 nm tube to tube spacing, is quite reasonable for the onset of such shortage.” Bo et al., at 182102-3.
Other shortcomings include the fact that the CNTs are dispersed in a host organic semiconducting matrix, which needs to be cured/baked post spin coating. The ultimate device performance is therefore gated by this starting host organic matrix. Organic semiconductors are known to have low starting material mobility, questionable lifetime, etc. In addition, the process singularly works with an organic host matrix and therefore is very limiting. Moreover, practical use of such pickup stick transistors would require completely new process tools, new fabs, new skill sets, etc.